The present invention relates to a semiconductor design technology and, more particularly, to a duty cycle correction circuit (DCC) for detecting and correcting a duty ratio of input clock signals.
Generally, a semiconductor device, such as a DDR SDRAM (Double Data Rate Synchronous DRAM), has been developed with large capacity, high speed and low current consumption. Particularly, in order to achieve high speed operation, the semiconductor device is designed to operate in response to a high-frequency external clock signal.
Recently, since the external clock signal operates at a high frequency of a few GHz and the semiconductor device operates in response to the high-frequency external clock signal, the quality of the external clock signal is very important. That is, if there are many jitter components in the input external clock signal or a duty ratio is far from 50:50, the operation timing of an internal circuit of the semiconductor device becomes wrong so that a stable circuit operation is not guaranteed.
In order to prevent such a problem, a duty cycle correction circuit for correcting the duty ratio to 50:50 is included in the semiconductor device.
FIG. 1 is a block diagram illustrating a conventional duty cycle correction circuit.
Referring to FIG. 1, the duty cycle correction circuit includes a buffer unit 110, a duty ratio detecting unit 130, a duty cycle correcting unit 150 and an oscillating unit 170.
The buffer unit 110 receives a positive external clock signal CLK_EXT and a negative external clock signal /CLK_EXT to output a positive input clock signal CLK_IN corresponding to the positive external clock signal CLK_EXT and a negative input clock signal /CLK_IN corresponding to the negative external clock signal /CLK_EXT. The positive external clock signal CLK_EXT and the positive input clock signal CLK_IN are nearly the same in phase. Also, the negative external clock signal /CLK_EXT and the negative input clock signal /CLK_IN are nearly the same in phase.
The duty ratio detecting unit 130 receives the positive input clock signal CLK_IN and the negative input clock signal /CLK_IN and compares them to output first and second detection signals DET_DCC1 and DET_DCC2 corresponding to the duty ratio of the positive and negative input clock signals CLK_IN and /CLK_IN.
The duty cycle correcting unit 150 receives the positive and negative input clock signals CLK_IN and /CLK_IN and corrects the duty ratio of the positive and negative input clock signals CLK_IN and /CLK_IN in response to the first and second detection signals DET_DCC1 and DET_DCC2. Thus, the finally outputted signals CLK_OUT and /CLK_OUT from the duty cycle correcting unit 150, of which the duty ratio is 50:50, have good quality.
The oscillating unit 170 generates an enable signal CTR_EN which enables the duty ratio detecting unit 130. The enable signal CTR_EN has a constant frequency. Thus, the duty ratio detecting unit 130 performs a detecting operation for a constant time which is repeated at a constant interval.
FIG. 2 is a circuit diagram illustrating the duty ratio detecting unit 130 of FIG. 1.
Referring to FIGS. 1 and 2, the duty ratio detecting unit 130 includes a differential I/O unit 210 for differentially receiving the positive input clock signal CLK_IN and the negative input clock signal /CLK_IN to output the first and second detection signals DET_DCC1 and DET_DCC2 corresponding to the duty ratio of the positive and negative input clock signals CLK_IN and /CLK_IN and an enable unit 230 for activating the differential I/O unit 210 in response to the enable signal CTR_EN.
A simple circuit operation of the duty cycle correction circuit will be described. First, the first and second detection signals DET_DCC1 and DET_DCC2 are in a high level by capacitors C1 and C2, respectively. The oscillating unit 170 outputs the enable signal CTR_EN having a constant frequency, and a first NMOS transistor NM1 of the enable unit 230 operates in response to the enable signal CTR_EN. Thus, the differential I/O unit 210 operates during a section in which the first NMOS transistor NM1 is turned on, that is, while the enable signal CTR_EN is in a high level.
The voltage levels of the first and second detection signals DET_DCC1 and DET_DCC2 change, according to the positive input clock signal CLK_IN and the negative input clock signal /CLK_IN. For example, if the section in which the positive input clock signal CLK_IN in a high level is longer than that in which the negative input clock signal /CLK_IN is in a high level, a second NMOS transistor NM2 is turned on longer than a third NMOS transistor NM3 so that there is much current which flows through the second NMOS transistor NM2. That is, the voltage level of the second detection signal DET_DCC2 becomes lower than that of the first detection signal DET_DCC1.
Then, the difference between the voltage levels of the first detection signal DET_DCC1 and the second detection signal DET_DCC2 becomes bigger during a detection section in the duty ratio detecting unit 130, and when the difference is more than a predetermined value, the differential I/O unit 210 amplifies and outputs the first and second detection signals DET_DCC1 and DET_DCC2.
The duty cycle correcting unit 150 (see FIG. 1) corrects the duty ratio of the positive and negative input clock signals CLK_IN and /CLK_IN which are inputted in response to the first and second detection signals DET_DCC1 and DET_DCC2.
As described above, the duty ratio detecting unit 130 performs a detecting operation in response to the enable signal CTR_EN having a constant frequency. Here, the longer an enable section of the enable signal CTR_EN is, the longer the duty ratio detecting unit 130 is enabled, allowing to perform a more precise detecting operation. The shorter the enable section of the enable signal CTR_EN is, the shorter the duty ratio detecting unit 130 is enabled, yielding a less precise detecting operation.
Meanwhile, the enable section of the enable signal CTR_EN should be differently designed according to the usage of the semiconductor device and the frequency of the external clock signals CLK_EXT and /CLK_EXT. In order to generate the enable signal CTR_EN having different enable sections per every semiconductor device, a designer should design the oscillating unit 170 to allow for such capability. Also, if an enable signal CTR_EN having a short enable section is used for a semiconductor device which needs a more precise detecting operation, the amplifying operation of the differential I/O unit 210 is not properly performed so that first and second detection signals DET_DCC1 and DET_DCC2 can be abnormally outputted. On the other hand, if an enable signal CTR_EN having a long enable section is used for a semiconductor device that needs a less precise detecting operation, the differential I/O unit 210 causes unnecessary current consumption.
Further, in case that the enable signal CTR_EN having a long enable section is used for the semiconductor device which needs a less precise detecting operation, since the semiconductor device cannot perform read and write operations before the duty of a clock is corrected, the unnecessarily long enable section of the enable signal CTR_EN becomes a factor in lowering the operation speed of the semiconductor device.